I am using AD9279-65EBZ and the ADC FMC interposer board to connect it to a Zedboard's FMC. I have designed a system to deserialize the data, send them to the ram on the fpga and then, via ethernet to the PC.
I set the AD9279 to output the test patterns, and the fpga captures them perfectly. But when I set the AD to output real data, I get errors in some of the captured samples. It seems like some of the sample bits are not correct, resulting in spikes in my captures.
For example, I connected one channel of the AD to a function generator, and set it to output a sine function of ~3Mhz. The AD is working at 40 MSPS. The capture can be seen below:
The question is what may cause the different behavior between capturing test patterns (they are always perfect) and capturing real data (there are some bit errors).
After deeper investigation, I found that there are also some wrong bits even at the test patterns. So the problem seems to be the capture of the digital data on the zedboard.
The LVDS signals from the AD9279 are connected to an IBUFDS and the output of it, goes straight to an ISERDESE for deserialization. I connected a debug core to the output of the ISERDESE and I found errors to some bits. I think that this means that probably the FPGA is receiveing weak or destorted digital signals.
So my question is, has anyone used the same setup (AD9279 -> ADC to FMC interposer -> Zedboard) succesfully?