What happens if the ADC is clocked below 3 MHz? Is 2 MHz okay?
You may have noticed in the datasheet that the minimum sample rate is 3Msps. This is the limit
under normal operation. Sample rates less than 3Msps are supported, but there is some 0.5 to 1.0 dB
degradation in SNR. For sample rates less than 3Msps, it is recommended that customers set SPI
Register 0x101 (Bit 2) = 1 (Run GCLK ON). This activates an oscillator which maintains the internal supply
doublers at low sample rates. The part will automatically detect a low sample rate and turn on GCLK by default, but this low-sample-rate threshold can vary by several MHz part to part and over temperature.
Please let me know if this answers your question adequately.
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