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Why have ADF4351 PFD input signals different frequencies?

Question asked by tilman on May 22, 2014
Latest reply on Jun 12, 2014 by icollins



during some debugging we we took a look at the input signals of a ADF4351 with an oscilloscope through the MUXOUT pin (see attached file). For my understanding of PLLs the input signals of a PFD should have the same frequency and phase in the locked state.


In the picture M1 is the reference input and has a frequency of 30.72 MHz as expected. But why has the N divider output (M2) a different frequency about 20MHz and where does that signal form come from? The ADF4351 says it is locked and the output frequency is also right.



reference input: 30.72 MHz Quartz

output frequency: 1800 MHz

INT value: 117:

FRAC value: 72

MOD value: 384

output divider: 2