I am using the BF518-EZKIT and have the ADC interfaced to the BF518 via the SPORT interface. I then use DMA to transfer blocks of data from the SPORT RX buffer into main memory.
I had been facing a problem that took me quite sometime to nail down. What I do not know is, what is causing this problem.
*pSPORT1_RCLKDIV = 0x0001; // 80/2*(1+1) = 20 Mhz *pSPORT1_RFSDIV = 0x0010; // FS after every 16-clocks or @1.176 Mhz (20/17)
When I set the RCLK_DIV to 0x0002 (or ~13.3 Mhz) , everything works fine. But when I set it to 0x0001 (20 Mhz), thats when the sampled data from ADC doesn't look the way it should.
I am using the Debug plot to visualize the input buffer once the DMA has transfered 256 blocks of data from the SPORT RX.
The following figure shows the anomalous behavior when RCLK_DIX = 0x0001; and a half rectified sine wave is applied to the ADC Channel. Observe the Y-axis, which essentially look like signal from cross-talk. Very weak.
Here is a Zoom in:
BTW, when no signal is applied, I see a flat line at 0, so that at least tells me that overall things are working.
Now, the way to fix this is to press the RESET button board, rebuild in VDSP++ (so it builds, links and loads). Once I do that, and change NOTHING in code, this is how this output looks: (Observe the Y-axis).
which is correct!
My question is: What happens when I press RESET that the adc (?) or its input or whatever seems to function correctly ?
All signals are applied to IN_VA1 and ADC's A0,A1,A2 = 000
Any insight is appreciated.