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ADAU1761 I2S slave mode with non-synchronous MCLK

Question asked by JohnAmpetronic on May 21, 2014
Latest reply on Jun 2, 2014 by JohnAmpetronic

Hello All


I have a quick question about the use of the ADAU1761 I2S port in slave mode.  I have tried the following experiment using an ADAU1761 and ADAU1701 evaluation kits.


I created a simple project that echoes the signals on the ADC0 and 1 of the ADAU1701 evaluation kit to its I2S serial port.  I then took the BCLK , LRCLK and ADC signals (by soldering wires to the 0402 resistors on the board!) to the serial port of the ADAU1761.  Note that I did not take the MCLK signal from the ADAU1701 board.


The experiment seemed to work but the lash-up caused a bit of noise on the LRCLK signal which created a noise problem with one channel.


Has anyone done this before?  The data sheet hints that it can be done with this:


"If the PLL of the ADAU1761 is not used, the serial data clocks must be synchronous with the ADAU1761 master clock input." (page 42 first paragraph).  The inference is that if the PLL is enabled then the serial clocks do not need to be generated by the sample MCLK that is clocking the ADAU1761.



Can anyone shed any light on this?  I thought that the master PLL derrived its clock (and hence the clock for the DSP) from the bit clock of the I2S data but now I think that the DSP is reading data as it is shifted in from the I2S port.