There is thread that explain 96kHz serial port operation for the ADAU1452.
But I'd like to make sure the register setting include core.
If my MCLKI is 24.576MHz and fs is 96kHz, according to the table 22 in the data sheet,
Pre-divider is 8 and FB divider is 96, then system clock will be 294.912MHz.
I now think that CLK GEN 1 x1 output rate is still 48kHz if I use default clock gen1 setting (N=1, M=6).
If so, should I set register 0xF401 (Start pulse) as 0b00011 (x2 rate) for core rate setting and 0xF20x for double rate?
Or change M=3, then 0xF401 should be 0b00010 (x1) and also 0xF201 should be base rate(x1)?
Which is good for operation?