My project uses 4 ADN4605s to pass the 4 TMDS signals to a ADV7619. So we can upstream switch between 2 video signals by changing the ADN4605s' routes (all 4), hitting a hardware update line that goes to all 4 ADN4605s, then look at the tmds/h/v locked bits in the ADV7619 to see when measurements are stable and can be read. First my algorithm waits for tmds locked, then h locked, then v locked, before reading the v measurements.
I'm finding that the v locked bit (either HDMI reg 7 or IO reg 6A, the raw bit), reports locked when it apparently is not, because the v measurements are wrong by sometimes 100s of lines.
When I add a 150 ms delay after the ADN4605 update, and then run the ADV7619 measurement algorithm, the measurements are reliable.
My question is why should I need this delay? According to the ADV7619 data sheet the v locked bit should tell me when the measurements are valid.
I see this same behavior even if I disable the 4605s' outputs, then delay 150 ms, then change the 4605 route and update, and then run the measurement algorithm. The ADV7619 seems to need the delay after the 4605 update.
I'm using basic operation of the ADV7619 (no free run or decimation -- PRIM_MODE[3:0]: 0X06, VID_STD[5:0]: 0X02)