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AD9361 Loop Test , Repeater Application

Question asked by sss on May 20, 2014
Latest reply on May 26, 2014 by sss

I check the following discussion.

 

http://ez.analog.com/thread/40747

AD9361 loopback ?

 

I am confused, can not understand the function of the register.

 

SPI Register 0x3F5—BIST Config2

D7—Data Port SP, HD Loop Test OE

D0—Data Port Loop Test Enable

 

I have understood as follows.

Is it Correct?

 

Q1)

Correct?

Tx Data input>>>TX1 or 2 Port Output >>>Coaxial cable Connect>>>Rx2 or 1 Port Input>>>Rx Data Output

 

Incorrect?

Rx2 or 1 Port Input>>>Rx Data Output>>>Cable Connect>>>Tx Data input>>>TX1 or 2 Port Output

DATA_CLK>>>FB_CLK

RX_FRAME>>>TX_FRAME

RXDATA>>>TX_DATA

 

Q2)

Correct?

0x3F5 [D7]

1:Half duplex mode enable

0:Full duplex mode enable? or other?

 

0x3F5 [D0]

1:Loop test enable?

0:What is this setting / situation?

 

Q3)

If I design using the AD9361 * 2pcs in digital repeater applications, what solutions would be the best ?

Antenna<>AD9361(1)<>FPGA? BBP?<>AD9361(2)<>Antenna

 

In the case of  frequency conversion type repeater equipment,

Is it enable, direct connect Data/CLK/Frame ,no FPGA or BBP ,using controler for SPI setting?

 

 

Please advice for me.

Thanks.

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