I have a few questions about ADDI7004.
Can we monitor DCR signal to know the SHP and SHD internal signal? How does DCR signal relate to SHP and SHD signal?
I would like to know when SHP and SHD start to sampling the input signal during CDS mode.
Can AFE of ADDI7004 handle input signal with negative voltage (-ve) without level-shifting the input signal?
Understand that there is a 23-cycle delay between the CCD input and the output.
Therefore, the input "N" signal will have its output after 23 cycles. We can know it by calculate 23 cycles. (as shown in Figure 21 in Datasheet)
However, is there any other way to know which data output belong to which input without calculating the 23 cycles?