Continue below customer's issue, http://ez.analog.com/thread/42117, I have come to field to check the issue. Basic connection is ADV7180->480i=>ADV8003=>SD encoder=>LCD display and TTL output to 7inch LCD panel.
Just as customer mentioned, bypass PVSP block, make primary input to SD encoder directly, the image is ok.
While if video stream go through PVSP for de-interlacing, the output from TTL output and SD encoder will be as below image. The odd-even field can be found dislocation. Embedded timing code or external HS/VS are same issue. According to this, can you advise how to verify this issue?