I am using multiple ADF4350 chips in a phased array application. All synthesizers output the same single frequency but their relative phase is reprogrammed periodically. I have already gotten the phase synchronizing and reprogramming working. My question has to do with the designing of the PLL loop filter. Here are the specs:
RF Out Freq = 153.8MHz
REF IN Freq = PFD = 6.152MHz
When using ADIsimPLL to calculate a loop filter, they suggest a loop bandwidth of 615kHz along with the 45 degree phase margin. That leads to loop filter components values that are impractically small (i.e. sub pF capacitors). I decided to make a compromise and go with a 200kHz bandwith. Again using ADIsimPLL to design the filter, the only way I could get practical component values was to bump up the charge pump current to the maximum 5mA. I installed the 200kHz filter on our custom boards and it seems to lock OK, but a problem is realized when 2 or more of the RF outputs are viewed simultaneously on the scope. With the charge pump set at 5mA there is an unacceptable amount of jitter between the two outputs (see attached photo). I tried reducing the charge pump current to the minimum 313uA and that reduced the jitter to a usable level, but it also lengthened the locking time considerably.
Is there any method of improving this jitter either with an better designed loop filter or with different register setting?