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Problem programming ADF4351 via SPI after SW power down

Question asked by tnjames on May 15, 2014

Hi

 

We are using the ADF4351 configured via an SPI interface implemented within an FPGA.  When not in use we wish to use the PD bit in R2 to minimise power (device CE is tied high).

 

Everything appears to work ok when writing to the SPI interface one word at a time (ie, with a delay of, eg, 100 ms between writes); we can retune and power down and power up.  However when we try and send the configuration words (R5 -> R0) 'back-to-back' the synth consistently fails to lock when exiting the power down state.  (We can then get it to lock by resending the R0 write after a delay.)  Whilst we can send individual writes during debug/development we would ideally like to minimise the time it takes to configure the synth in our application.

 

Are there any delays we need to be aware of when programming the synth from the power down state?  There is nothing in the datasheet apart from the SPI timings which are all being met (SPI clock is 4 MHz, with a couple of clock cycle periods between writes).  For example do we need a min delay between deasserting the PD bit (and enabling the VCO) in our R2 write before we should write to R0?  The datasheet does mention the use of an internal reference used when automatically selecting the VCO + range.  Is our problem that we are attempting to configure the VCO before this reference has stabilised yielding an invalid solution?  If so how long does the regulator take to stabilise - it is not in the datasheet.

 

Thanks in advance

 

Tim

 

PS Having posted this question subsequently stumbled across the ADF4351 initialisation post essentially asking the same question.  However the verified answer given refers to stabilisation of the board power supplies.  In our case the supplies are already up and we are trying to bring the ADF4351 out of power down.  The post implies a 2 us delay between R1 and R0 writes should be sufficient but if possible (and assuming our problem is due to an internal reference power up delay starting from the end of our R2 write (where we clear the PD bit)) would prefer a recommended minimum R2 LE rising (PD cleared) to R0 LE rising (tune kicked off) delay.  Also request that this figure is added to the datasheet.  Presumably the same delay constraint also would apply to CE asserted to R0 LE rising?

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