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x4 (96kHz) problem on SHARC 21161N Ez-Kite

Question asked by EbuBad on Aug 14, 2010
Latest reply on Aug 15, 2010 by vishwanath

I changed the value of DAC_CONTROL1 to 0x002

and ADC_CONTROL1 to 0x040

both read_reg and write_reg

when i just changed ADC value , no prob.

but when changing DAC reg. i cant see nothing on osc.

but i cant get the 48 kHz frequency

 

i just wanted to try how can i get 48 kHz signal ?

and SHARC have a AD1852 DAC

i dont know how i can get 96 kHz signal too

i changed the JP6 but nothing changed

always 24kHz max.

 

How can i fixed it ?

thanx for ur helps

regards.

 

 

int tx_buf3a[TX_BUF3A_LEN] = //program register commands
                {    DAC_CONTROL1 | WRITE_REG | 0x000,   
                    DAC_CONTROL1 | WRITE_REG | 0x000,   
                    DAC_CONTROL2 | WRITE_REG | 0x000,  
                    DAC_VOLUME0  | WRITE_REG | 0x3FF,
                    DAC_VOLUME1  | WRITE_REG | 0x3FF,
                    DAC_VOLUME2  | WRITE_REG | 0x3FF,
                    DAC_VOLUME3  | WRITE_REG | 0x3FF,
                    DAC_VOLUME4  | WRITE_REG | 0x3FF,
                    DAC_VOLUME5  | WRITE_REG | 0x3FF,
                    ADC_CONTROL1 | WRITE_REG | 0x000,   
                    ADC_CONTROL1 | WRITE_REG | 0x000,
                    ADC_CONTROL3 | WRITE_REG | 0x000,   
                    ADC_CONTROL2 | WRITE_REG | 0x380,  
                    ADC_CONTROL2 | WRITE_REG | 0x380,
             
                    ADC0_PEAK_LEVEL | READ_REG | 0x000,
                    ADC1_PEAK_LEVEL | READ_REG | 0x000,
                    ADC2_PEAK_LEVEL | READ_REG | 0x000,
                    ADC3_PEAK_LEVEL | READ_REG | 0x000,
                    ADC_CONTROL1     | READ_REG | 0x000,
                    ADC_CONTROL2     | READ_REG | 0x000,
                    ADC_CONTROL3     | READ_REG | 0x000 };

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