I am modifying the axi_ad9361 core to add some additional functionality (generate I-Q samples based on input data, process received samples etc.), and I am hoping to get some visibility into the status of my code by setting some registers and then using the IIO Oscilloscope tool Debug tab to read them (I am using Zedboard+FMCOMMS2).
However, even before I make any mods, I am not sure how to read register values set by the ad9361 core in the IIO Oscilloscope debug tag. For example, I see that some register addresses show values in the SPI address space, or actual hw registers on the board, but what about registers only managed in the verilog code? For example, can I see registers like vdma_frmcnt (address 8'h21) or drp_status (address 8'h1d) - these are defined in adi_common/hdl/verilog/up_dac_common.v in the oscilloscope? I am not interested in these specific registers - what I want to know is how to set registers and make them visible to the oscilloscope so I can see some code status in software. Also, the up_addr is 8 bits wide, but only a small number of addresses seem to be used currently. Can I map the remaining addresses to my own registers, and see their values in the oscilloscope tool?