We are using a custom board in whch AD9361 is interfaced to FPGA baseband. In receive mode we are getting high DC content in the received signal, which is causing a false sync in the synchronizer module. Can this happen because of any misalignment in the A/D,D?/A operation, or LO leakage. Can anyone help us to determine the issue? What test procedures should be tried out to find the source of the DC content?