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Clock Generation and Distribution (AD9577)

Question asked by AlexCoh on May 11, 2014
Latest reply on May 13, 2014 by AlexCoh

Hi,

I want to generate and to distribute 128MHz clock to ADC/DAC(AD9707,AD9251). (I need 3-LVDS and 1-CMOS outputs)

I'm using AD9577.

Ref clock is SINE=26MHz (50 ohm 0dBm from OCXO)

OUTPUT clock LVDS=128MHZ (CMOS=128MHz as an option).

 

Questions:

  1. Can I provide a Sine ref clock to AD9577 or should it be "square wave"?
  2. My ref clock source is 50 ohm--> 0dBm, and AD9577 refclk input requires 2V for "1", how can I know the internal resistance of REFCLK port?
    I want to be sure 0dBm@50ohm is enough (0dBm=1mW, P=Vout*Vout/R, Vout=SQRT{1mW*50}=0.22V@50ohm at Ref clock output).

 

Thank you.

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