- Standard LVDS Termination: 3-resistor transmitter, 1 resistor receiver termination.
This is used in the AD9434 eval board and suggested in the Altera Arria II handbook, pg 150 (attached for reference). This is the LVDS style of termination he is familiar with and has used in the past many times (with Actel FPGAs):
- Receiver-only Termination: 100 ohm parallel termination specified in the AD9434 datasheet:
He is leaning towards terminating the AD9434 side of the bus using the 3-resistor Bourn's network and optionally replacing it with a zero to 47 ohm series network essentially giving them the second option.
Any thoughts you can share on this method would be greatly appreciated. Any pitfalls?...