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21489 SPI Master Boot: MISO Level Problem

Question asked by babazaroni on May 8, 2014
Latest reply on May 15, 2014 by Jithul_Janardhanan

I'm trying to boot the 21489 EZ-Board chip using spi master boot from a  host processor.   The problem I am seeing is the MISO bit  of the  21489, starts to drive after about 31 cycles of the spi clock. It should  remain an input to accept the boot kernel.  The spi clock continues to  run for 384 32 bit words.  The boot mode selector sw4 is set to 1, spi  master boot mode.  The MOSI bit is working correctly, as 0x3000000 is  sent out during the first 32 cycles.  I'm using DPI2 as the MISO bit via pin 27 of the expansion interface.  This is the default pin route setting after a reset.

 

So why does the MISO bit start to drive?

 

I've attached a pic of 3 scope captures.  Pic 1 is the 21489 miso bit unconnected, which shows it start to driving after 31 bits.  Pic 2 is the host miso bit showing normal levels.   Pic 3 is the 21489 and host miso bits connected, showing the clash.

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