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AD6657 synchronous capture problem

Question asked by Malek on May 8, 2014
Latest reply on May 19, 2014 by Malek

Hi,

I am using for a sensor array the AD6657 AD converter evaluation board together with the HSC-ADC-EVALCZ FPGA based capture board.

I would have two questions for my specific application:

  • I need to sample the four channels synchronously to evaluate the phase between the channels. This does not apply using the standard FPGA .bin file. This can be observed using the Visual Analog software and 4 windows for plotting the data. I tried to use another file named „high speed synchronous“. But no data was captured at all. My question is whether it is possible to use the four channels simultaneously. It would sufficient to capture data for 3 us using a 200 MSps sampling rate.
  • It would be great if I can preprocess the data in the available Virtex-4 FPGA. Would it be possible to provide the vhdl/Verilog project so that I can apply changes to it.

 

thank you

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