I am running the AD9361 FMCOMMS2 Board on a ZC702 Xilinx Board with the latest GitHub no-OS SW drivers and latest GitHub HDL code for Vivado. The AD9361 is configured to run in 2tx2rx mode and I am using a TX/RX sample rate of 61.44MHz which is what I ultimately would like to use for my application.
I have been using the Cyclic DMA to send I/Q data to the device's DAC which in turn is generating a sine wave output at an offset from the LO frequency. With a sample rate of 61.44MHz, if I load 32 samples of I data for TX and 32 samples of Q data for TX with values offset by 90 degrees, I get a sine wave as expected but the frequency offset from the LO frequency I am seeing does not stack up with the sample rate? I would expect to see a sine wave at an offset of (61.44MHz/32)=1.92MHz, what I actually see is a sine wave at an offset of 1.536MHz. I have also tried 256 point and 1024 point sine wave data sets for which I would expect; (61.44/256)=240KHz carrier offset and (61.44MHz/1024)=60KHz carrier offset respectively but the output I see is 192KHz and 48KHz offsets respectively.
This is consistent at least in that if you multiply the output offsets by 1.25 then you get the expected frequency but I can not see how this multiply by 0.8 of the clock is occurring?
Any suggestions would be much appreciated...
Hopefully I am being dumb and missing something here!?
Thank you in advance.