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UG-237 Issue

Question asked by HankZ on May 7, 2014
Latest reply on May 8, 2014 by HankZ

On page 26 of 204, for the table of values listed for pixel port output modes, there is a note 2 that indicates the following:

The 0x54, 0x94, 0x95, 0x96 modes registers should be set as follows:

DPLL Map, Register 0xC3 to Register 0x80. DPLL Map, Register 0xCF to Register0x03. IO Map, Register 0xDD to Register 0xA0. IO Map, Register 0xBF[0] = 0 (CP_COMPLETE_BYPASS_IN_HDMI_MODES disabled).

None of these registers exist in the ADV7619 Register Map, Rev.0, July 2013.  It's also unclear what is meant by the phrases register 0xXX to register 0xXX.  Should say something like data 0xXX to register 0xXX.