ADM1293 has support internal hold time of at least 300ns? If yes, the master provide 0ns to 299ns internal delay is ok? ADM1293 report data to master can measure the hold time of at least 300ns? Thanks!
The i2c interface of the ADM129x devices is complaint with the i2c specification.
In the specification it stated:
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL.
to be complaint with this we would recommend the master to support the minimum hold time of 300ns.
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