I'm working through this reference design project but I'm running into errors:
I'm using the ML605 development board with Xilinx ISE 14.7. I have some experience with the Xilinx FPGA design flow, but not enough to make it through this setup on my own.
The first thing I did was run the download.bat script that comes with the project. This ran to completion without a problem. I don't have an external clock source to connect to the development board however, so I did not see the teraterm screen shot output that was posted in the tutorial. I assume this is because there is no clock driving the ADC. So I moved on from this part.
The second thing I did was to open the system.xmp project and export the design to SDK. As I understand it, this would generate all the pcores needed by the design without having to use coregen separately. The process ran for quite a while until it error-ed out in the place and route phase with the following:
ERROR:PhysDesignRules:2506 - Incorrect placement for a BUFR component. BUFR
axi_adc_1c_0/axi_adc_1c_0/USER_LOGIC_I/i_adc_1c/i_adc_wr/i_adc_if/i_clk_gbuf in clock region CLOCKREGION_X0Y4 is
driven by a CCIO adc_clk_in_p in clock region CLOCKREGION_X1Y2. The BUFR should be placed in the same clock region as
the CCIO or the CLOCK_DEDICATED_ROUTE constraint should be used on the net
ERROR:Pack:1642 - Errors in physical DRC.
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
I'm not sure what to do at this point. Did I skip something that was necessary? Any help is greatly appreciated.