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Certain clock/sample rate settings do not work as reported by software

Question asked by daniel.meinzer on May 5, 2014
Latest reply on Jun 16, 2014 by mhennerich

FMCOMMS-2 with FPGA evaluation board and No-OS software from Analog.

 

These settings work fine and we see the 61.44 msps sample rate on our data bus. (We are using LVDS)

/* Rate & BW Control */

// BBPLL_FREQ,     ADC_FREQ, R2_FREQ, R1_FREQ, CLKRF_FREQ,   RX_SAMPL_FREQ,

{983040000, 245760000, 122880000, 61440000, 61440000, 61440000},//uint32_t    rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{983040000, 245760000, 122880000, 61440000, 61440000, 61440000},//uint32_t    tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

 

These settings appear to configure properly, and report themselves as correct in the software (tx_samp_freq? =61440000), however the device appears to be configured for a much higher sample rate.  For example, LVDS DATA_CLK is running > 300 MHz instead of 244 MHz, it still seems to be operational though.

/* Rate & BW Control */

// BBPLL_FREQ,     ADC_FREQ, R2_FREQ, R1_FREQ, CLKRF_FREQ,   RX_SAMPL_FREQ,

{737280000, 368640000, 122880000, 61440000, 61440000, 61440000},//uint32_t    rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{737280000, 368640000, 122880000, 61440000, 61440000, 61440000},//uint32_t    tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies

 

Are these all valid rxtx clock chain settings?  Is this expected behavior?

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