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AD9361 VDD_ITFC_on while VDDx_off

Question asked by Ed_V Employee on May 2, 2014
Latest reply on May 5, 2014 by tlili

It appears the AD9361 isn't picky about the power-up sequence, but I'm considering leaving the VDD_INTERFACE powered while the +1.3V rails remain OFF until selectively enabled sometime later. Will this be a problem for the AD9361? And might it cause unpredictable states on the digital pins?

 

And under such circumstances, if we have an external clock coming in to the XTAL pin while +1.3V is down, do you expect that to cause a problem?

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