I am having issues running the vivado reference design. I have everything building correctly except that a few of the block design pins are not connected. This was the design in the hdl git directory so I am assuming those connections can remain disconnected for now. However, when I write the bitstream and run the example no-OS drivers I am not getting anything out of the card. Is there something I am missing. I know these details are vague but I don't know how to approach this issue. And to add to this I implemented some of my own vhdl code along side the FMCOMMS2 zed and my system seems to run fine not sure if that helps. (simple serializer for future modulation schemes).