I've created a custom board that has, among other components, an AD9739 DAC. The custom board connects to Xilinx's ZC706 Zynq evaluation board. I'm feeding the DAC a 1 GHz sample clock from a PLL on the custom board, and its data interface is connected to Zynq.
Right now, I'm trying to get the DAC to output data, and I'm running into difficulties. I'm running through the SPI start-up sequence suggested on the datasheet. At the very end, when I've re-started the data receiver, wait 135,000 cycles of the 250 MHz (1GHz/4) clock coming from the FPGA, and read back its status on reg 0x21, I get the desired value of 0x09 usually, indicating the data receiver is locked and tracking.
However, if I wait even about 1 second or more, and read back register 0x21 again, I get a value of 0x0B, indicating that somewhere along the line, I've lost lock. And if I try and output something onto the DAC, I don't see anything. This behavior is consistent.
I have an idea of what the problem is, but I wanted to see if I could get some verification. Back when I was designing the custom board, I had neglected to route the DCO to the FPGA. I didn't think this was a big deal because I assumed as long as my DCI clock was 1/4 the sample clock, I'd be okay. However, after having this problem, I'm wondering if the lack of the DCO feedback is what's causing the data receiver to lose lock.
I know another cause for losing lock is if there's a lot of jitter in the sample clock, the DCI clock, or both. However, the sample clock jitter is in the 100's of fs rms, and when I measure the jitter of the DCI clock, it's about 40 ps rms. From what I've read in the DAC datasheet, the DAC should be able to tolerate such a combined jitter. So again, I'm wondering if because I don't have the DCO feedback, there might be some small frequency offset between the DCI and the sample clock that's causing the problem?
Any help with this would be greatly appreciated.