I have a problem with the ADF4351 PLL, it is setup as follows:
A 100 MHz ref clock should generate a 2.4 GHz clock used by two AD9739, one connects to RFoutA, the other to RFoutB.
The PLL claims that it is locked.
The SPI registers is setup as follows:
When I change target frequency to 2.2 GHz with the following SPI setup:
(only change R) it works fine, both RFout A and RFout B have the same frequency.
I don't understand what is happening, I have reviewed the SPI setup, especially R to turn on AUX output with +5dBm etc.
Please assist, I'm stuck!
Regards -- Pontus
PS PLL schematic, the clocks go directly to the DAC, terminated close to the DAC pins with 100 Ohm.