AnsweredAssumed Answered

ADF4351 outputs half the frequency on AUX (RFout B)

Question asked by pontus on Apr 30, 2014
Latest reply on May 26, 2014 by pontus

Hi,

I have a problem with the ADF4351 PLL, it is setup as follows:

A 100 MHz ref clock should generate a 2.4 GHz clock used by two AD9739, one connects to RFoutA, the other to RFoutB.

 

The PLL claims that it is locked.

The SPI registers is setup as follows:

R[5]=0x00580005
R[4]=0x008C83FC
R[3]=0x00E004B3
R[2]=0x19009FC2
R[1]=0x00008011

R[0]=0x00300000

 

When I change target frequency to 2.2 GHz with the following SPI setup:

R[5]=0x00580005
R[4]=0x008C83FC
R[3]=0x00E004B3
R[2]=0x19009FC2
R[1]=0x00008011

R[0]=0x002C0000

(only change R[0]) it works fine, both RFout A and RFout B have the same frequency.

 

I don't understand what is happening, I have reviewed the SPI setup, especially R[4] to turn on AUX output with +5dBm etc.

 

Please assist, I'm stuck!

 

Regards -- Pontus

PS PLL schematic, the clocks go directly to the DAC, terminated close to the DAC pins with 100 Ohm.

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