AnsweredAssumed Answered

Phase relationship between REF Input and OUTx output signals (AD9520-x).

Question asked by ysuzuki on Apr 30, 2014
Latest reply on Mar 17, 2016 by pkern

Hello,

 

I have a question about AD9520-x clock genelator.

The condition and configuration are followings.

 

Reference Input : 61.44MHz @ REF2

R,A,B counters nSYNC pin reset : Synchronous reset

Internal Zero-delay mode

OUT0~2  : 245.76MHz

OUT3~5  : 122.88MHz

OUT6~8  : 61.44MHz

R Counter : 384

Prescaler : 2

B Counter : 768

PFD Freq. : 160kHz

VCO Freq. : 1474.56MHz

PLL Loop BW : 1kHz

VCO Divider : /1

DIVIDER 0

Divide Ratio : 6

Phase Offset : 0

Ignore SYNC : obeys chip-level SYNC signal

DIVIDER 1

Divide Ratio : 12

Phase Offset : 0

Ignore SYNC : obeys chip-level SYNC signal

DIVIDER 2

Divide Ratio : 24

Phase Offset : 0

Ignore SYNC : obeys chip-level SYNC signal

 

I have expected REF Input(61.44MHz) and OUT6 signal has same phase.

But the phase relatioship between these signals has three position after SYNC signal.

(The resolution of the phase difference is PI/2)

 

I think I can get same phase relationship by setting "R,A,B Counters nSYNC pin reset"

register to "Synchronous reset".

Of course, when I set OUT0 to 61.44MHz I can get same phase between REF.

 

Is it necessary to set the frequency of OUT0 to 61.44MHz to get same phase?

 

Thank you,

Best regards.

 

ysuzuki

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