Please let me know the function of IO_REG_05 0x05 and 0x05 register.
Those are undocumented bits and should be left at their default values.
Noise level of ADC around ADV 7842 is reduced when ADV 7842 IO_REG_05[7:6] is set to 11.
In this setting, output image from ADV7842 is unstable but output image is stable when LLC_DLL_PHASE[4:0] is modified.
Could you tell me the function of IO_REG_05[7:6] because of verifying above adequacy.
Let me see if I can get more information on this register
We need more information for design and evaluation now.
Please let me know about function of this register.
I just asked the ADV7842 expert again about this register.
Changing IO 0x05[7:6] may adversely effect pixel output format or timing. They need to be left at their recommended values.
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