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AD9739 SPI issues

Question asked by Z.Yang on Apr 29, 2014
Latest reply on Jun 2, 2014 by danf



I have experienced some problems with AD9739 SPI control and I would like to find out if these are known issues or maybe I did something wrong.


1. The IRQ bits in register 4 (IRQ) cannot be cleared. I checked register 0x21 and 0x2a and verified that both the data receiver and Mu controller are locked and tracking before I write a 0 to the register 3 (IEN). Then I write a 0xa to register 3 to re-enable the IRQ for receiver lock lost and Mu controller lock lost. However the corresponding bits in register 4 are still set. I even tried to write a software reset to register 0 but the IRQ bits are still not affected.


2. I clock the DAC at 2.4 GHz and use the 600 MHz DCO as the system clock for the driving circuits. When I set the register 0x25 to 0x80 as suggested in the start-up sequence, it will cause a reset on some units. I guess it's because it generates a glitch on the DCO clock output and the glitch varies on different chips so some will be big enough to trigger a system reset. If I just leave the register 0x25 at the default value 0, will there be any side effect?


3. During the test I discovered that if I read two registers back-to-back (several microseconds between two complete read operations with /CS back to high after finish), the second register cannot be read properly. I have to add some delay (1 ms worked but haven't tried to find the minimum value) in between the two read operations in order to read both registers correctly. The minimum time to start the next read is not specified in the datasheet. Where can I find this information?


Thanks for your help!