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NEED ASSISTANCE FOR DECOMPRESSION IN JDATA MODE

Question asked by Baathu on Aug 5, 2010
Latest reply on Aug 10, 2010 by DaveD

Am trying to decompress the compressed frame but am not GETTING valid for a long time.

What am doing is pumping the compressed data from NIOS cpu to a fifo where transfer is 32-bit wide. But the jdata takes 8-bit each when valid is asserted. The valid is asserted for a short time and then its not getting asserted for a long time,by this time the fifo is getting full and the data is overflown.

Does the adv212 looks for a header in the starting itself and if some blank frame data like 0xFFFFFFFF are sent in the beginning, could it be problematic. the code what am using is.......

 

CAN YOU PLZ CHECK MY PARAMETERS IF ANYTHING ARE WRONG

 

//SET PLL_HI AND PLL_LO
adv212_write_direct_reg (GRS_MAIN_HDATA_CTRL_0_adv212_1_PLL_HI,0x0008);
wait_time(90000);
adv212_write_direct_reg (GRS_MAIN_HDATA_CTRL_0_adv212_1_PLL_LO,0x0004);
wait_time(90000);
//ENTER NO BOOT HOST MODE
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_BOOT,0x008A);
wait_time(90000);
//-------------set busmode and miscellaneous mode
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_BMODE,0x0005);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_MMODE,0x0005);//09
//-------------LOAD FIRMWARE--------------------------
unsigned long mem_data;
unsigned long i;
unsigned long firmware_address = 0x00050000;
unsigned long addr_onchip; /////////////////////// onchip memory address
addr_onchip = GRS_MAIN_SDRAM_0_BASE+0x00008000;
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_STAGE,0x0005);
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_IADDR,0x0000);
for (i=0;i<=32768;i=i+4 )
  {
   mem_data         = reg_read(addr_onchip);
   addr_onchip      = addr_onchip + 4;
   adv212_write_firmware(mem_data,GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA);
  }
printf("loading firmware completed \n");
//SOFT REBOOT
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_BOOT, 0x008D);
//setting bus and mmode
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_BMODE,0x0015);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_MMODE,0x0005); 
//-----------setting decode parameters------------
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_STAGE,0x0005);
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_IADDR,0x7F00);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0X0100);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0X0003);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0X0000);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0X0000);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0X0011);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0X0001);
///////////////////////////////////////////////////////////////////////////////////
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_STAGE,0xFFFF);
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_IADDR,0x1408);
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0x001A);
//Enable EIRQIE[1] (DFTH) and EIRQIE[10] (SWIRQ0)
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_EIRQIE, 0x0400);//400      
printf("checking for interrupt \n");
//check EIRQFLG[10] is asserted or not
while(reg_read(GRS_MAIN_HDATA_CTRL_0_adv212_1_EIRQFLG) != 0x040F){//0x040F
for(i=0;i<10000;i++){
  printf("reading from add: 0x%08X, data 0x%08X \n",GRS_MAIN_HDATA_CTRL_0_adv212_1_EIRQFLG , reg_read(GRS_MAIN_HDATA_CTRL_0_adv212_1_EIRQFLG));
}
printf("interrupt not occured--reload DECODE firmware\n");
break;
}
printf("interrupt completed\n");
// CHECK DECODE FIRMWARE CORRECTLY LOADED
reg_read_comp(GRS_MAIN_HDATA_CTRL_0_adv212_1_SWFLAG,0xFFA2);
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_STAGE,0xFFFF);
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_IADDR,0x1408);
reg_write(GRS_MAIN_HDATA_CTRL_0_adv212_1_IDATA,0x001B);
adv212_write_direct_reg(GRS_MAIN_HDATA_CTRL_0_adv212_1_EIRQFLG,0xFFFF);

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