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BF561 PPI Sync. Problems

Question asked by Tommy on Aug 5, 2010
Latest reply on Sep 6, 2010 by Tommy

ADI Support,

 

we have a customized board with BF561 where we have connected a Aptina MT9V024 sensor to PPI0 with 8 bits. We have connected the Horizontal Sync to FSYNC1 and Vertically sync.  to FSYNC2 and also the Pixel Clock to the PPI_Clock input. The problem we have is the DMA transfer does not transfer the data when we use the external Frame sync only on internal Frame Sync on PPI control register settings.

 

The PPI Control register is configured as followed.

 

*pPPI0_CONTROL = 0x019D;

that means:

PORT_EN     1

PORT_DIR    1

XFR_TYPE   3

PORT_CFG  1 Internal Frame Sync

FLD_SEL      0

PACK_EN     1

DMA32          1

SKIP_EN       0

SKIP_E0       0

DLEN             0

POLC            0

POLS             0

 

When we change to

*pPPI0_CONTROL = 0x01AD;

 

the DMA transfer does not start at all.

 

I have also changed the POLC and POLS Bit but this does not change anything. With the Oszilloskope I could see that the HSync and VSync and also the PPI_CLK is comming correctly from the Sensor and are connected to the processor.

 

What options do we have to see what can cause the missing start of the DMA transfer with external HSync and VSync trigger.

 

Any suggestion!

 

Regards

Tommy

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