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AD9361 - ZedBoard OS problems with Matlab/Simulink

Question asked by Quamstar on Apr 24, 2014
Latest reply on Apr 24, 2014 by rgetz

Hey,

 

at the moment i try to explore the advantages of programming the ZC7020 with Matlab/Simulink using HDL and Embedded Coder. Therefor i found a simple Example (http://www.mathworks.de/de/help/hdlcoder/examples/getting-started-with-hw-sw-codesign-workflow-for-xilinx-zynq-platform.html). At this time i still use the Operationssystems provided by Analog to communicate with the AD9361. And there seems to be some Problem because of the following errors:

 

 

1. In this particular Example, there is the Option of an External Control via Embedded Coder out of Simulink. Therefor you need to do Generate Software Interface Mode in the Workflow advicer of Matlab. When try to do this there pops up an error, like in the attached picture. I would say that there are now right to write, but i connected with root and password analog.

 

2. If i generate the HDL-Code (I can skip the Problem discribed in 1.) and Programm the SoC-FPGA the OS seems to be shut down, there are no more connection available to the Board and the Display also switch of.

 

 

So in the next step i will try to use an alternative OS from Xilinx, but later on i will need to programm the FPGA without interrupting and shutting down the OS (by Analog)

 

Thanks for your help

Jan

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