AnsweredAssumed Answered

Sigma Running out of Steam?

Question asked by electrojim on Aug 2, 2010
Latest reply on Aug 5, 2010 by MagicRuB

I'm running an ADAU144x on the A/D development board with the usual USB interface.  The development board includes a provision to force-clock one of the 1938 codec chips at 192kHz via SPI.  The design has a Main board that contains seven Hierarchy boards, plus a couple of first-order filter modules and a Multiplexer module also on the main board for a test function.  The entire circuit is set to operate at a 192kHz sampling rate, and all rate-sensitive modules have been checked to make sure that the rate has been propagated throughout the system.  Everything looks right, and once I compile and view the output file I see that I'm using less than 50% of DSP resources.

 

One of my outputs off the main board is a 20kHz sinewave, generated directly with a Source/Oscillator/Sine Tone.  The trouble is, the actual frequency coming out is one-fourth of that, or 5kHz.  If I start removing Hierarchy boards one-by-one and recompiling, at some point the output frequency switches to one-half of what it should be, or 10kHz.  If I remove even more Hierarchy boards, so that only a couple of the seven are left, the frequency pops up to 20kHz where it belongs.  When 'removing' boards one-by-one, the wannabe 20kHz waveform undergoes a visible change when the circuit is recompiled.  You can see on a scope that it's on the hairy edge of changing to the next higher fraction of 20kHz, exhibiting a 'hump' in the waveform that looks as if it wants join in and create a signal at 2X the current frequency.  Sure enough, dump one more Hierarchy board and that's what it does: 5kHz becomes 10kHz, or 10kHz becomes 20kHz.

 

The high sampling rate is necessary because the design processes some signals up in the 60kHz range.  But just for drill, I reset all the sampling rates to 48kHz.  With all seven Hierarchy boards running, the 20kHz output is 10kHz.  I need to remove only a few to get 20kHz out.  It's almost as though (thinking now in hardware/analog terms) the clock is being loaded and needs some unity-gain buffers in there.  Ideas, anyone?

Outcomes