Hello,

I'm using an AD-FMCOMMS3 board connected to a Xilinx KC705 Kintex board running a microblaze processor.

I downloaded the NO-OS drivers and made the needed adaptations (custom SPI and LVDS Interface) and i can transmit and receive RF data.

In the default_init_param i only changed the following lines:

{960000000, 120000000, 120000000, 60000000, 60000000, 60000000},//uint32_t | rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies | |

{960000000, 120000000, 120000000, 60000000, 60000000, 60000000},//uint32_t | tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies | |

30000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz | ||

30000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz |

0, | //gc_rx1_mode *** adi,gc-rx1-mode | ||

0, | //gc_rx2_mode *** adi,gc-rx2-mode |

I have two main problems:

1. The configuration frequencies displayed are close but not the same as the requested frequencies.

For example, when I request a BBPLL frequency of 960,000,000 Hz the driver log displays 990,235,753 Hz as seen below:

ad9361_reset: by SPI

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_setup

ad9361_set_dcxo_tune : coarse 8 fine 5920

ad9361_set_trx_clock_chain

ad9361_bbpll_set_rate: Rate 960000000 Hz Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 123779469 Hz Parent Rate 990235753 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 123779469 Hz Parent Rate 123779469 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 123779469 Hz Parent Rate 123779469 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 123779469 Hz Parent Rate 123779469 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 61889734 Hz Parent Rate 123779469 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 61889734 Hz Parent Rate 123779469 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 61889734 Hz Parent Rate 61889734 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 61889734 Hz Parent Rate 61889734 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 61889734 Hz Parent Rate 61889734 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 61889734 Hz Parent Rate 61889734 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rssi_setup

2. When transmitting a simple square wave signal (same signal in I and Q) with the same settings stated above to a short (10cm) SMA loopback cable, I receive a very noisy signal in the RX channel regardless of the square wave frequency.

Any help on how to debug these problems will be appreciated.

Gilad

Hi Gilad,

The problem reported by the other user was found after some changes were made to the code in order to make it compatible with Visual Studio 2008.

What version of Xilinx tools are you using?

Thanks,

Dragos