We are working on a custom board based on AD9361. RF board is interfaced to an FPGA base band board.
What we have observed is, whenever the AD9361 is moving into RX mode, RX FRAME signal immediately goes HIGH.
We are using CMOS mode, (RX_FRAME_P connected, RX_FRAME_N not connected), and RX_FRAME is configured for LEVEL Mode operation.
RX_FRAME signal stays continuously HIGH, throughout the Receive period (when 0x017 shows 18). When FPGA drives AD9361 to TX mode or ALERT, (0x017 shows 16, or 15), RX_FRAME signal goes LOW.
P0,P1 ports have some data, (seems like ADC noise as the amplitude of these are 30-40 LSBs or less), this data is passed on to the FPGA continously as RX FRAME is always ON. I was expecting RX_FRAME signal to go HIGH, only when there is a valid data. Is my understanding correct? Do i have to set any threshold values or something to make RX_FRAME high only when i have a valid input?