AnsweredAssumed Answered

Why high levels on selected ADV7612P video output pins in blanking period?

Question asked by Aphraton on Apr 17, 2014
Latest reply on Apr 17, 2014 by GuenterL

Hello!

Is it correct, that ADV7612P is producing High logic level during both horizontal and vertical blanking periods only on lines P20 ( pin 46 ) and P7 ( pin 61 ) if ADV7612P is set in 422 YCrCb 16bits with Embedded Syncs mode?

In all other 14 lines the level during horizontal and vertical blanking periods is Low as expected.

On screenshots below ( from logic analyser in FPGA ) these high levels are present in [7] and [12] data lines.

Video_IN_HDMI_1.PNG

Video_IN_HDMI_2.PNG

Here is the init procedure for ADV7612:

 

> $98 $FF $80 ; I2C Reset

* 10          ; 10ms pause

> $98 $FD $44 ; CP

> $98 $FA $6C ; EDID

> $98 $F9 $64 ; KSV

> $98 $FB $68 ; HDMI

 

> $98 $00 $1E ; VID_STD = 1080P

> $98 $01 $15 ; Prim_Mode =101b HDMI-COMP 50Hz

> $98 $02 $F5 ; CSC

> $98 $03 $80 ; 16 Bit ITU656 SDR Mode

> $98 $04 $60 ; OP_CH_SEL + 27MHz

> $98 $0B $44 ; Power up part

> $98 $0C $42 ; Power up part

> $98 $14 $7F ; Max Drive Strength

> $98 $15 $80 ; Disable tristate

> $98 $19 $83 ; LLC DLL phase

> $98 $33 $40 ; LLC DLL Enable

> $44 $BA $01 ; Set HDMI FreeRun

> $64 $40 $81 ; Disable HDCP 1.1 features

> $68 $9B $03 ; ADI recommended setting

> $68 $00 $09 ; Set HDMI Input Port B (BG_MEAS_PORT_SEL = 001b)

> $68 $02 $03 ; Enable Ports A & B in background mode

> $68 $83 $FC ; Enable clock terminators for port A & B

> $68 $6F $0C ; ADI recommended setting

> $68 $85 $1F ; ADI recommended setting

> $68 $87 $70 ; ADI recommended setting

> $68 $8D $04 ; LFG Port A

> $68 $8E $1E ; HFG Port A

> $68 $1A $8A ; unmute audio

> $68 $57 $DA ; ADI recommended setting

> $68 $58 $01 ; ADI recommended setting

> $68 $75 $10 ; DDC drive strength

> $68 $90 $04 ; LFG Port B

> $68 $91 $1E ; HFG Port B

 

Input HDMI-stream is according to VIC#31 ( 1080p50 ) with 48 kHz PCM audio.

I did not test other ADV7612 modes.

EDID is internal and I used it from the end of ADV7612-VER.2.9c.txt file.

This issue doesn't affect ADV7511 connected directly through FPGA to ADV7612, the picture on ADV7511 is OK.

But I intend to use blanking period for my own purposes and I am confused by this fact.

What can cause this strange behaviour?

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