The ADAU1701 has a maximum sample rate of 192kHz. However the datasheet does not specify a minimum sampling rate (that I can see anyway). If I use a lower crystal input frequency or select a lower divide ratio, I can clock the device at a lower rate. I realise I cannot get any more instructions due to memory restrictions but I need a lower sampling rate for improved accuracy at lower frequencies.
Is it allowed to run the A/D and D/A systems at 24kHz on the ADAU1701? I know this cannot be done on the evaluation hardware but it can easily be arranged on custom hardware.
The only clue is in the datasheet. The normal 12.288MHz clock is used in the 256 x Fs configuration. 12.288MHz is 81.38ns clock period which is within the 73-488ns allowed for this configuration on the datasheet (page 7).
For the 64 x Fs mode the maximum clock period is 1953ns equating to a clock of 512032 kHz. Dividing this by 64 gives 8000.512Hz which tends to indicate that the converter can work down to 8kHz?