I am attempting to use the AD9760 DAC to prototype a design. It is connected to a Spartan-3E FPGA which is providing the data bits and clock at 3.3V to the DAC circuit. I also have the analog voltage at 3.3V provided by a separate power supply. I'm measuring the output on a Tektronix oscilloscope. I'm using a simple ramp signal as output to test the DAC circuit and range of the analog output. When the DAC is connected to the FPGA, the analog output observed on IOUTA is a constant 700mV (IOUTB = 40mV). The sample clock provided to the DAC is currently 1MHz. I have probed each of the data pins at the AD9760 pin to confirm the signal levels upon entry to the DAC and all measure 3.3V, as expected, and are toggling as expected. The clock signal was also confirmed to be clean and 3.3V. Since the data bits are supposed to be latched in parallel on the rising edge of the sample clock, I have tested the operation by shifting the data bits 90 and 180 degrees out of phase with the clock so the data is definitely stable when sampled by the DAC and confirmed the setup times are not being violated.
While debugging this circuit, I also detached the data lines from the FPGA and manually connected them to either power (3.3V) or ground. The FPGA is still providing the sampling clock at 1MHz. Here are a few of my observations:
Data_in: "1111111111" = 720mV on IOUTA
Data_in: "1100000000" = 480mV on IOUTA
Data_in: "1000000000" = 360mV on IOUTA
Data_in: "0000000000" = 40mV on IOUTA
Seeing a change in the analog output level when the data bits are manually configured (versus driven by FPGA logic) leads me to believe I have a problem with the data being latched from the FPGA? However, I've confirmed via the oscilloscope that the data bits are toggling and that the data is stable on the rising edge of the DAC sample clock.
I've attached a drawing of my circuit. Any help would be greatly appreciated.