My design work is to used AD9361 with Fast AGC mode, I disabled the low power threshold checking in state 2 of Fast AGC mode. And it means that I use AGC Lock level mode in state 2.
My question is that when set register 0x101 as 0A(h) and 0x118 as 3F(h). I took some measurement with input power range from (-56 ~ -92.8dBm) but I got different resultant RSSI.
Should this Fast AGC mode use AGC lock Level as ultmiate goal in adjusting the gain index? If so, it should produce constant RSSI value even it has different received input power.