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AD9361 : Single Port Full Duplex Mode with CMOS level ,Timig Diagram

Question asked by TomHsu on Apr 14, 2014
Latest reply on Apr 20, 2014 by TomHsu

Dear Sir :

      We are high interesting in AD9361 for now project, according to the application,

        I want to configure digital interface of AD9361 as single port Full Duplex mode with CMOS level,

        please refer to figure 5(see attched file page 2). the setting of registers as below

           Register address 0x010 set as 0xC8

           Register address 0x011 set as 0x00

           Register address 0x012 set as 0x24

      Thus AD9361 should be under 1T1R, SDR, FDD and single port.

      The question is what is the timing relation between clock and data in transmit/receive interface?

       I couldn’t find the relevant timing chart in data sheet, so I draw the timing chart of data and clock

       as attched file page 3, is it correct ? If it is not correct, please show me the exact timing chart.

 

       In these condition 

       Receive data path functional timing as attched file page 3

        Transmit data path functional timing as attched file page 3

 

        Thank You for your help.

 

Best Regards

Tom hsu

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