Yagami

96 kHz operation for ADAU1452 serial ports

Discussion created by Yagami on Apr 13, 2014

I had been experimenting with running the ADAU1452's serial ports at 96 kHz and I ran into a bit of confusion. However, I've successfully figured out how to set up the system for 96 kHz operation, and I figured I would share this information with the community in case it is helpful.

 

Let's say I want to run a serial port at a 96 kHz sample rate. The serial ports can be individually configured to get their clocks from Clock Generator 1, Clock Generator 2, or Clock Generator 3.

 

However, it looks like there are two places where the clock frequency can be set...

 

Reg. 0xF021 (Clock Gen1 N)

and

Reg. 0xF201 & 0xF211 (Serial Port Control)

 

I was originally confused if I should change the setting of Clock Gen 1, or if I should simply change the settings of individual serial ports.

 

It turns out that 0xF021 Clock Gen1 N sets the "base" value for the clock generator. You use this to scale the clocks by small amounts. For example, you could change from 48 kHz to 44.1 kHz using Clock Gen 1 N, or you could change to 49 kHz, or 41 kHz, or 38 kHz, or any other "strange" clock frequency.

 

Remember that every clock generator actually generates 5 sample rates simultaneously. This means that setting Clock Gen 1 to 48 kHz (which is the default setting) will generate 48 kHz, 96 kHz, 192 kHz, 24 kHz and 12 kHz.

 

There are 3 clock generators and each of them generate 5 sample rate (frame) clocks simultaneously. This means that at any given time, 15 sample rate clocks are being generated.

 

You can see this on page 28 of the datasheet, in figure 18.

ScreenHunter_13 Apr. 13 20.08.jpg

 

0xF201 / 0xF211 control the individual serial ports and allow you to choose one of the 15 sample rate clocks available. Since by default, clock gen 1 is already generating both 48 kHz and 96 kHz, in order to use 96 kHz on some of your serial ports, you simply need to select Clock Gen 1 and 2*Fs in the appropriate registers.

 

You can see on page 108 that these registers contain a CLK_DOMAIN bitfield and an FS bitfield.

[4:3] CLK_DOMAIN selects from one of the three clock generators.

[2:0] FS selects one of the 5 sample rate clocks from the corresponding clock generator.

ScreenHunter_12 Apr. 13 20.08.jpg

 

So, to use the 96 kHz generated from clock generator 1, you should set [4:3] CLK_DOMAIN to 0b00 (Clock Generator 1) and set [2:0] FS to 0b011 (Double rate of selected clock generator).

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