After working in Xilinx Platform Studio for the last few months, I changed over to Vivado a few days ago and built a Vivado project for an FMCOMMS2 on a zc702 platform using the reference design files from the repository. I am getting an error during synthesis because the design assumes that the AXI IIC IP has bidirectional scl and sda connections, but it does not. I opened up the project in XPS and the AXI IIC IP (older version) does have bidirectonal scl and sda connections. So, somewhere along the way they were removed from the AXI IIC block, and I think that bidirectional buffers need to be added between the AXI IIC block and the external ports. Am I correct in this judgement, or did I miss something in the design? Thanks.