I am using the AD9434 on the an capturing a 600 MHz signal (on the HSC-ADC-EvalC board with 500 Msps capability), while using a 320 MHz clock for the ADC.
For additional background I have calculated, based on the input impedance to the ADC and available signal power the full scale for the 1000 ohm input impedance is ~-5dBm. (I am an RF guys so I think in terms of power). The published SNR on this device is ~62 dB ( I have degraded the SNR slightly from the published SNR of 63.5at 450 Hz in)
The basic question relates to theoutputs I obtain where the choices of input format settings, the second dialogue box in the template. The two potential choices I have looked at are the "offset binary" and the "two's Complement".
I find with the offset binary setting, when I change the input signal from a clean, calibrated 600 MHz source (Agilent 8657a), by 50 dB, the captured signal in dBFS changes what seem to be the appropriate 50 dB. However the noise floor captured is down around -115 dBm which seems way to low considering the full scale reading and SNR.
When I choose the "Two's complement" format, the noise floor looks right around -75 dBFS, but the captured signal level does not track and in fact if makes it seems that the ADC is virtually at full scale with 600 MHz signal levels all the way down to <-40dBm input.
I would like to capture both the FFT processed signal and the real ADC magnitude vs time files from the 64k FIFO.
Any additional insight would be greatly appreciated for capturing the real data.