could you confirm that in standalone mode (no SPI/I2C) there is no way to make the ADAU1966 work at 96kHz sample rate?
Interesting. On the same day I got two questions with the identical wording asking about the identical thing. One from you here on EngineerZone and one through our central applications center. Often customers will ask the same question in two places so I figured it was you. I would be glad to review your schematic if you like. But, on to your question.
Regarding the tests you did where you fed the DAC 96kHz signals and all you got was full scale noise. There is probably a signal integrity issue that increasing the clock frequencies caused it to show up. This may be able to be improved however, it does not matter as far as running at 96kHz in standalone mode. I had time today to go into the lab and run some experiments using an evaluation board. My results is that I did get signal and it sounded good but the noise floor did go up a great deal. It was not the same results you obtained but it was not acceptable performance. I suspect that there is an internal clock that is running too high causing clocking noise and clocking errors. When I switched the DAC_CTRL0 register for 96kHz sampling rate and then changed the MCS setting, PLL_CLK_CTRL0[2:1] register, to ob10 I got clean audio at 96kHz. In this setting the dividers are properly set for 96kHz and 256xfs MCLK.
The DAC_CTRL0 fs setting is used for setting the BCLK rate to the proper setting when using TDM modes but is also used in conjunction with the MSC setting to set the internal MCLK dividers.So even though it should all scale up and work, the internal clocks will be running at twice the rate and that is not a good thing to do.
So this is the long answer. The short answer is No, you cannot run at 96kHz in standalone mode.
This is something that we do not characterize and test. The sample rate range that the part is set for in standalone mode is 32-48kHz. If you setup the part to act as a slave you could feed it 96kHz clocks and everything would scale up and probably work but we cannot guarantee there will not be other issues. This is something I would have to try in the lab to see if there are any audio artifacts or other issues. I can investigate this if you like but it will be several days before I can perform some experiments. The MCLK dividers are all set for 256x fs so you would have to supply it with 24.576MHz MCLK.
I did have a look at your schematic. From a quick scan the design looks fine. I do not see the 0.1uf caps for the power supply pins but I assume they are elsewhere in the schematic. You will need one for each power pin.
One other thing I noticed. You are using two output amplifiers for the differential signal. If they were voltage followers it would be fine but I see you are referencing them individually to ground. I think you will have poor noise performance with this topology. It is best to either use a differential input stage to convert the signal to single ended or use voltage followers that do not reference to ground. I know that eventually you will be going into a differential stage and the noise should cancel out but then you are depending on these two stages being precisely the same to obtain good CMRR. So be prepared that you may have to modify these output stages should you find the noise level to be too high.
Hi Dave, thanks.
I tried what you're saying, just moving the clock to 24.576MHz, 256 x fs, fs = 96kHz. DAC is outputting a full scale noise also with all zeros input, like something has gone crazy.
Datasheet table 12 states that you have to set DAC_CTRL0[2:1] to "01" and PLL_CLK_CTRL0[2:1] to "10" to operate at 96kHz/24.576MHz, while standalone values are "00" and "00".
If you have any news, please let me know... We are ending up with an ugly rework to connect an SPI to the part in order to get it work at 96k!
By the way, I didn't provide you a schematic... maybe you got confused with someone else schematic.
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