On, the evaluation board reference design from the file ADV7403_EVAL_NOTE_MINI_REVA_aug_07.pdf, I am almost done tweaking my design based on this reference design. Now, I am thinking about layout and looking at the sample 4-layer layout, I have a couple questions:
1. Referring to pages 19-22 of the document, they have the layers in the following sequence:
- Layer 1 - Top layer - signal layer SMT stuff mostly
- Layer 2 - ground layer
- Layer 3 - power plane
- Layer 4 - Bottom layer - signal layer
The top layer looks fine, no questions there, but the remaining layers are giving me some trouble to make out without tediously following power lines.
I am trying to figure out what the designer is doing here exactly?
Layer 2 for example, this is the ground layer, looks to me like there is NO sloting at all and he has common'ed all the GND, digital ground, analog gnd, etc. a SINGLE ground plane without regions -- thus agnd, dgnd, iognd, etc. all go to this plane GND, no questions asked.
Layer 3 - the power plane is curious, its hard to see if power is actually being fed to the slotted regions, so am I correct in this? Are each of the regions getting various feeds from the various supplies? Its very hard to tell, or is this yet another ground plane/faraday shield setup? I think he is feeding from layer 4, the bottom?
Layer 4 - the final and bottom layer has more signal traces, but also looks like its running the majority of the power to the chips on the top layer and then via'ing thru to layer 3?
Other than overlaying these gerber layers together with transparency, its hard to see what is going where. I usually don't do this and keep all my power in the power plane and try not to run the rails on top and via down, I prefer to run power straight out of the regulator outputs on the power plane itself, but whatever --
Anyway, is my assement correct of this design? top signal, merged ground, slotted power plane, being fed from 4th layer, 4th layer with signal and power feeds?