Input Signal : 4.5 MHz (FPGA to AD9361)
LO : 220MHz
LO Amplitude : -56dB (observed in signal analyzer)
Main signal level : Delta of -14dB
Here we can observe that LO is higher than then main input signal level. What should be done to increase the power level of input signal and decrease the power level of LO??
Next, we tried to increase the power level by changing the value of 073 register in AD9361. It is said that the resolution of the values in the register is 0.25dB/LSB. But when we give values, it doesn't work so in terms of 0.25dB/LSB.
Here are the values we observed:
Value in Register 073(in hex) Attenuation(dB)
Clearly this doesn't follow the values indicated for the register. Are we doing any mistakes here? Or is it going wrong somewhere?
Can somebody provide explanation, as well as guide us with the values for proper functioning??
Kindly give us information