What is the procedure to troubleshoot?
What is your source and video format? How are you isolating the PLL power supply from the digital core supply? What circuit do you have on the ELPF pin?
I have come to believe that the 7184 can not be used to digitize to CCIR 601 and then be serialized to SMPTE259 directly. I think that there needs to be some kind of PLL or clock generator circuit inbetween the Decoder and the Serializer in order to remove jitter from the 27 MHz clock to satisfy the SMPTE specs.
I originally thought that the low frequency jitter that I was seeing on the SMPTE serial waveform was caused by a malfunction in the 7184. I have done a lot of experiments and then realized that the REC 601 standard is specified only to 3 ns or 3000 ps. The input to the serializer needs to have a 27 MHz clock with a jitter spec of about one tenth of that (like 300 ps). My guess is that the VCXO in the 7184 that creates a 27 MHz clock from a 28.63636 MHz crystal, is just not stable enough for direct SMPTE conversion. I believe that the 7184 is working as well as it can but that is not good enough for my application.
I would like to know if there is anything wrong with my analysis. Is there another Analog to Digital converter that I could use that would be better suited?
Unfortunately the ADV7184 will not work in such an application.
The ADV7184 LLC (line locked clock) will not meet the required jitter specification of the Gennum serialiser.
To meet the Gennum serialiser jitter specification, a decoder with Frame TBC (e.g. ADV7802) must be used.
Thank you for the reference to the ADV7802. Just one problem....I found
this device on the Analog Devices website but there is no link to the
specification. I would need to have a look at the specification before
making a decision to use the part.
Sierra Video Systems
Can you please work with your local FAE/disti FAE to obtain the documentation.
They should be able to furnish you with the required info.
I still have a similar problem with the ADV7802 - Jitter is too high. We have a de-jitter circuit that can correct the normal jitter but there are periodic jumps in jitter that overwhelm our correction.
I have tried everything possible on the PVCC - improved filtering and replace the supply with a bench supply, but this makes no difference at all so I don't think it is a power supply problem.
As well we accidentally had the wrong value cap in the ELPF2 an 82 nF instead of the recommended 820 nF in series with the 160 ohm resistor and jitter was much better with the 82 nF cap but the periodic jumps were still there.
I noticed that the 28.3636 MHz xtal is sensitive to touch - I can modulate the jitter with my finger, but it is stable when I don't touch it.
Are you using the Time Base Correction feature (with external memory)?
We are using external memory but I don't know if we are using the 'Time
Base Correction' feature. How do I determine that?
I also looked at an earlier design with the ADV7189B and it has the same
periodic frequency shift on LLC2, but the output is de-jittered adequately.
As David said, the Frame TBC feature must be enabled to get the LLC jitter to a level that is suitable for a Gennum serializer.
Please review section 7.17 in the ADV7802 hardware manual.
Excellent - thanks! That cleans it up nicely with just one mystery
We accidentally put a 82 nF cap in series with the 160 ohm resistor on
ELPF2. With the 82 nF cap the jiitter (after our de-jitter) is steady at
0.16 or 0.17 UI but if I use the recommended 820 nF cap the jitter
I like the results with the 82 nF better.
Unfortunately we can't stand over any ELPF components other than the recommended.
These are selected over skew material, voltage and temperature during the evaluation of the part.
With the TBC turned on and the 82 nF cap I have 0.16 UI jitter.
With the TBC turned on and the 820 nF cap I have 0.30 UI jitter or more.
How much jitter should I expect with the 820 nF cap?
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