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Porting PmodAD1 to the microzed board

Question asked by flatmax on Apr 3, 2014
Latest reply on Aug 14, 2014 by flatmax

Hi there,

 

I am trying to port the PmodAD1 reference design to the microzed board.

I can produce a bitstream which only has the axi_dma and axi_ad7476 modules, as well as the relevant axi_interconnect modules.

The bitstream loads ok ... from what I see.

 

I also think I have a valid dts.

 

The interrupts I see in Xilinx xps are : 91 and 90

So I have mapped the dts interrupts to 59 and 59 .... see the dts below.

 

When Linux tries to boot, it has trouble when looking for the dma :

xilinx-dma 40400000.axidma: unable to request IRQ -22

Unable to handle kernel NULL pointer dereference at virtual address 00000004

pgd = c0004000

[00000004] *pgd=00000000

Internal error: Oops: 805 [#1] PREEMPT SMP ARM

Modules linked in:

CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0 #1

task: ec86d1c0 ti: ec86e000 task.ti: ec86e000

PC is at xilinx_dma_of_probe+0x60c/0x6e0

LR is at __lock_is_held+0x38/0x5c

 

 

The relevant parts of my dts look like so :


fpga_axi: fpga-axi@0 {


compatible = "simple-bus";


#address-cells = <0x1>;


#size-cells = <0x1>;


ranges;

 

 



fpga_clock: fpga_clock {



compatible = "fixed-clock";



#clock-cells = <0>;



clock-frequency = <200000000>;


};

 

 



axi_dma_0: axidma@40400000 {



#address-cells = <1>;



#size-cells = <1>;



#dma-cells = <1>;



compatible = "xlnx,axi-dma";



reg = <0x40400000 0x10000>;



dma-channel@40400000 {




compatible = "xlnx,axi-dma-s2mm-channel";




interrupts = <0 59 0x4>;




xlnx,datawidth = <0x40>;




xlnx,sg-length-width = <23>;




xlnx,include-dre = <0x0>;



};


};

 

 



ad_adc_0: AD7476A_1@79020000 {



compatible = "xlnx,axi-ad-adc-1.00.a";



reg = < 0x79020000 0x10000 >;



dmas = <&axi_dma_0 0>;



dma-names = "ad-adc-dma";



adc-name-id = "ad7476a";



adi,streaming-dma;


};

 

 



axi_dma_1: axidma@40440000 {



#address-cells = <1>;



#size-cells = <1>;



#dma-cells = <1>;



compatible = "xlnx,axi-dma";



reg = <0x40440000 0x10000>;



dma-channel@40440000 {




compatible = "xlnx,axi-dma-s2mm-channel";




interrupts = <0 58 0x4>;




xlnx,datawidth = <0x40>;




xlnx,sg-length-width = <23>;




xlnx,include-dre = <0x0>;



};


};

 

 



ad_adc_1: AD7476A_2@79040000 {



compatible = "xlnx,axi-ad-adc-1.00.a";



reg = < 0x79040000 0x10000 >;



dmas = <&axi_dma_1 0>;



dma-names = "ad-adc-dma";



adc-name-id = "ad7476a";



adi,streaming-dma;


};

 

 






trigger: trigger@0 {



compatible = "iio-trigger-hrtimer";


};

};

 

Here is my mhs file :

# PORT SWs_8Bits_TRI_IO = SWs_8Bits_TRI_IO, DIR = IO, VEC = [7:0]

# PORT LEDs_8Bits_TRI_IO = LEDs_8Bits_TRI_IO, DIR = O, VEC = [7:0]

# PORT BTNs_5Bits_TRI_IO = BTNs_5Bits_TRI_IO, DIR = IO, VEC = [4:0]

PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]

PORT processing_system7_0_PS_SRSTB = processing_system7_0_PS_SRSTB, DIR = I

PORT processing_system7_0_PS_CLK = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK

PORT processing_system7_0_PS_PORB = processing_system7_0_PS_PORB, DIR = I

PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK

PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK

PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO

PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO

PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO

PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO

PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O

PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]

PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]

PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO

PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST

PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]

PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]

PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]

PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]

PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO

PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO

PORT int_1_pin = int_1, DIR = I, SIGIS = INTERRUPT

PORT int_2_pin = int_2, DIR = I, SIGIS = INTERRUPT

PORT int_3_pin = int_3, DIR = I, SIGIS = INTERRUPT

PORT int_4_pin = int_4, DIR = I, SIGIS = INTERRUPT

PORT axi_ad7476_0_data0_i_pin = axi_ad7476_0_data0_i, DIR = I

PORT axi_ad7476_0_data1_i_pin = axi_ad7476_0_data1_i, DIR = I

PORT axi_ad7476_0_sclk_o_pin = axi_ad7476_0_sclk_o_pin, DIR = O, SIGIS = CLK

PORT axi_ad7476_0_cs_o_pin = axi_ad7476_0_cs_o_pin, DIR = O

PORT axi_ad7476_slave_0_cs_o_pin = axi_ad7476_slave_0_cs_o_pin, DIR = O

PORT axi_ad7476_slave_0_data1_i_pin = axi_ad7476_slave_0_data_1_i_pin, DIR = I

PORT axi_ad7476_slave_0_sclk_o_pin = axi_ad7476_slave_0_sclk_o_pin, DIR = O, SIGIS = CLK

PORT axi_ad7476_slave_0_data0_i_pin = axi_ad7476_slave_0_data_0_i_pin, DIR = I

 

BEGIN processing_system7

PARAMETER INSTANCE = processing_system7_0

PARAMETER HW_VER = 4.02.a

PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF

PARAMETER C_USE_M_AXI_GP0 = 1

PARAMETER C_EN_EMIO_CAN0 = 0

PARAMETER C_EN_EMIO_CAN1 = 0

PARAMETER C_EN_EMIO_ENET0 = 0

PARAMETER C_EN_EMIO_ENET1 = 0

PARAMETER C_EN_EMIO_I2C0 = 0

PARAMETER C_EN_EMIO_I2C1 = 0

PARAMETER C_EN_EMIO_PJTAG = 0

PARAMETER C_EN_EMIO_SDIO0 = 0

PARAMETER C_EN_EMIO_CD_SDIO0 = 0

PARAMETER C_EN_EMIO_WP_SDIO0 = 0

PARAMETER C_EN_EMIO_SDIO1 = 0

PARAMETER C_EN_EMIO_CD_SDIO1 = 0

PARAMETER C_EN_EMIO_WP_SDIO1 = 0

PARAMETER C_EN_EMIO_SPI0 = 0

PARAMETER C_EN_EMIO_SPI1 = 0

PARAMETER C_EN_EMIO_SRAM_INT = 0

PARAMETER C_EN_EMIO_TRACE = 0

PARAMETER C_EN_EMIO_TTC0 = 0

PARAMETER C_EN_EMIO_TTC1 = 0

PARAMETER C_EN_EMIO_UART0 = 0

PARAMETER C_EN_EMIO_UART1 = 0

PARAMETER C_EN_EMIO_MODEM_UART0 = 0

PARAMETER C_EN_EMIO_MODEM_UART1 = 0

PARAMETER C_EN_EMIO_WDT = 0

PARAMETER C_EMIO_GPIO_WIDTH = 64

PARAMETER C_EN_QSPI = 1

PARAMETER C_EN_SMC = 0

PARAMETER C_EN_CAN0 = 0

PARAMETER C_EN_CAN1 = 0

PARAMETER C_EN_ENET0 = 1

PARAMETER C_EN_ENET1 = 0

PARAMETER C_EN_I2C0 = 0

PARAMETER C_EN_I2C1 = 0

PARAMETER C_EN_PJTAG = 0

PARAMETER C_EN_SDIO0 = 1

PARAMETER C_EN_SDIO1 = 0

PARAMETER C_EN_SPI0 = 0

PARAMETER C_EN_SPI1 = 0

PARAMETER C_EN_TRACE = 0

PARAMETER C_EN_TTC0 = 0

PARAMETER C_EN_TTC1 = 0

PARAMETER C_EN_UART0 = 0

PARAMETER C_EN_UART1 = 1

PARAMETER C_EN_MODEM_UART0 = 0

PARAMETER C_EN_MODEM_UART1 = 0

PARAMETER C_EN_USB0 = 1

PARAMETER C_EN_USB1 = 0

PARAMETER C_EN_WDT = 0

PARAMETER C_EN_DDR = 1

PARAMETER C_EN_GPIO = 1

PARAMETER C_FCLK_CLK0_FREQ = 100000000

PARAMETER C_FCLK_CLK1_FREQ = 142857132

PARAMETER C_FCLK_CLK2_FREQ = 200000000

PARAMETER C_FCLK_CLK3_FREQ = 20000000

PARAMETER C_INTERCONNECT_S_AXI_HP1_MASTERS = axi_dma_0.M_AXI_S2MM & axi_dma_1.M_AXI_S2MM

PARAMETER C_USE_S_AXI_HP1 = 1

PARAMETER C_NUM_F2P_INTR_INPUTS = 2

BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1

BUS_INTERFACE S_AXI_HP1 = axi_interconnect_3

PORT MIO = processing_system7_0_MIO

PORT PS_SRSTB = processing_system7_0_PS_SRSTB

PORT PS_CLK = processing_system7_0_PS_CLK

PORT PS_PORB = processing_system7_0_PS_PORB

PORT DDR_Clk = processing_system7_0_DDR_Clk

PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n

PORT DDR_CKE = processing_system7_0_DDR_CKE

PORT DDR_CS_n = processing_system7_0_DDR_CS_n

PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n

PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n

PORT DDR_WEB = processing_system7_0_DDR_WEB

PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr

PORT DDR_Addr = processing_system7_0_DDR_Addr

PORT DDR_ODT = processing_system7_0_DDR_ODT

PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB

PORT DDR_DQ = processing_system7_0_DDR_DQ

PORT DDR_DM = processing_system7_0_DDR_DM

PORT DDR_DQS = processing_system7_0_DDR_DQS

PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n

PORT DDR_VRN = processing_system7_0_DDR_VRN

PORT DDR_VRP = processing_system7_0_DDR_VRP

PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0

PORT FCLK_CLK1 = processing_system7_0_FCLK_CLK1

PORT FCLK_CLK2 = processing_system7_0_FCLK_CLK2

PORT FCLK_CLK3 = processing_system7_0_FCLK_CLK3

PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N

PORT FCLK_RESET1_N = processing_system7_0_FCLK_RESET1_N

PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0

PORT S_AXI_HP1_ACLK = processing_system7_0_FCLK_CLK1

PORT IRQ_F2P = axi_dma_0_s2mm_introut & axi_dma_1_s2mm_introut

END

 

 

BEGIN axi_interconnect

PARAMETER INSTANCE = axi_interconnect_1

PARAMETER HW_VER = 1.06.a

PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0

PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N

PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0

END

 

 

BEGIN axi_interconnect

PARAMETER INSTANCE = axi_interconnect_3

PARAMETER HW_VER = 1.06.a

PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 1

PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET1_N

PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0

END

 

 

BEGIN axi_dma

PARAMETER INSTANCE = axi_dma_0

PARAMETER HW_VER = 6.03.a

PARAMETER C_SG_LENGTH_WIDTH = 23

PARAMETER C_INCLUDE_MM2S = 0

PARAMETER C_INCLUDE_SG = 0

PARAMETER C_S_AXIS_S2MM_TDATA_WIDTH = 32

PARAMETER C_S2MM_BURST_SIZE = 256

PARAMETER C_GENERIC = 1

PARAMETER C_INCLUDE_S2MM_DRE = 0

PARAMETER C_INCLUDE_S2MM_SF = 1

PARAMETER C_BASEADDR = 0x40400000

PARAMETER C_HIGHADDR = 0x4040ffff

BUS_INTERFACE S_AXI_LITE = axi_interconnect_1

BUS_INTERFACE M_AXI_S2MM = axi_interconnect_3

BUS_INTERFACE S_AXIS_S2MM = axi_ad7476_0_S_AXIS_S2MM

PORT m_axi_sg_aclk = processing_system7_0_FCLK_CLK0

PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK0

PORT m_axi_s2mm_aclk = processing_system7_0_FCLK_CLK0

PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0

PORT mm2s_introut = axi_dma_0_mm2s_introut

PORT s2mm_introut = axi_dma_0_s2mm_introut

END

 

 

BEGIN axi_ad7476

PARAMETER INSTANCE = axi_ad7476_0

PARAMETER HW_VER = 1.00.a

PARAMETER C_BASEADDR = 0x79020000

PARAMETER C_HIGHADDR = 0x7902ffff

BUS_INTERFACE S_AXI = axi_interconnect_1

BUS_INTERFACE S_AXIS_S2MM = axi_ad7476_0_S_AXIS_S2MM

PORT s_axi_aclk = processing_system7_0_FCLK_CLK0

PORT data_0_i = axi_ad7476_0_data0_i

PORT data_1_i = axi_ad7476_0_data1_i

PORT sclk_o = axi_ad7476_0_sclk_o_pin

PORT cs_o = axi_ad7476_0_cs_o_pin

PORT ref_clk = processing_system7_0_FCLK_CLK0

PORT rx_clk = processing_system7_0_FCLK_CLK3

PORT s_axis_s2mm_clk = processing_system7_0_FCLK_CLK0

PORT adc_start_out = axi_ad7476_ADC_START

PORT dma_start_out = axi_ad7476_DMA_START

END

 

 

BEGIN axi_dma

PARAMETER INSTANCE = axi_dma_1

PARAMETER HW_VER = 6.03.a

PARAMETER C_SG_LENGTH_WIDTH = 23

PARAMETER C_INCLUDE_MM2S = 0

PARAMETER C_INCLUDE_SG = 0

PARAMETER C_S_AXIS_S2MM_TDATA_WIDTH = 32

PARAMETER C_S2MM_BURST_SIZE = 256

PARAMETER C_GENERIC = 1

PARAMETER C_INCLUDE_S2MM_DRE = 0

PARAMETER C_INCLUDE_S2MM_SF = 1

PARAMETER C_BASEADDR = 0x40440000

PARAMETER C_HIGHADDR = 0x4044ffff

BUS_INTERFACE S_AXI_LITE = axi_interconnect_1

BUS_INTERFACE M_AXI_S2MM = axi_interconnect_3

BUS_INTERFACE S_AXIS_S2MM = axi_ad7476_1_S_AXIS_S2MM

PORT m_axi_sg_aclk = processing_system7_0_FCLK_CLK0

PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK0

PORT m_axi_s2mm_aclk = processing_system7_0_FCLK_CLK0

PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0

PORT mm2s_introut = axi_dma_1_mm2s_introut

PORT s2mm_introut = axi_dma_1_s2mm_introut

END

 

 

BEGIN axi_ad7476_slave

PARAMETER INSTANCE = axi_ad7476_slave_0

PARAMETER HW_VER = 1.00.a

PARAMETER C_BASEADDR = 0x79040000

PARAMETER C_HIGHADDR = 0x7904ffff

BUS_INTERFACE S_AXI = axi_interconnect_1

BUS_INTERFACE S_AXIS_S2MM = axi_ad7476_1_S_AXIS_S2MM

PORT s_axi_aclk = processing_system7_0_FCLK_CLK0

PORT ref_clk = processing_system7_0_FCLK_CLK0

PORT rx_clk = processing_system7_0_FCLK_CLK3

PORT s_axis_s2mm_clk = processing_system7_0_FCLK_CLK0

PORT cs_o = axi_ad7476_slave_0_cs_o_pin

PORT data_1_i = axi_ad7476_slave_0_data_1_i_pin

PORT sclk_o = axi_ad7476_slave_0_sclk_o_pin

PORT data_0_i = axi_ad7476_slave_0_data_0_i_pin

PORT adc_start_in = axi_ad7476_ADC_START

PORT dma_start_in = axi_ad7476_DMA_START

END

 

 

Any help would be greatly appreciated.

 

thanks

Matt

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